For a data-processing system, a memory device for storing information is very important. There are two kinds of semiconductor memory devices. One kind is volatile; volatile memory devices lose their contents when power is interrupted. Another kind is nonvolatile; nonvolatile memory devices retain their contents despite power failure. The applications of nonvolatile memory devices have been restricted by various practical difficulties, such as those relating to the capability to change the content of stored data, and to limitations on manipulations during use.
On the other hand, nonvolatile memory devices which adopt the MOS floating gate structure have been widely used. These devices use a floating gate, which is made of conductive material and is electrically insulated from the substrate, and the gate is capacitively coupled with the substrate. Therefore a MOS transistor, capable of detecting the charged condition of the floating gate, can be formed. According to the existence of charge within the floating gate, the MOS transistor can be in the conducting state (ON) or in the non-conducting state (OFF), and hence it can keep the data of "1" or "0". As a mechanism to inject charge into or to remove charge from the floating gate, hot electrons generated by avalanche breakdown or by the tunneling effect are used, respectively.
Among these nonvolatile semiconductor memory devices, the demand for EEPROM in which data is electrically erased and programmed has increased.
A 128K flash EEPROM semiconductor memory device using double polycrystalline silicon technology was disclosed at the IEEE International Solid-State Circuits Conference held in 1987. (See pp. 76-77 of conference digest.)
As shown in FIG. 1 and FIG. 2, the cell structure of the conventional flash EEPROM has an electrically insulated first polycrystalline silicon layer 4 on the substrate 1 in the vicinity of the drain region, between the drain region 3 and the source region 2, as a floating gate. Moreover the cell structure also has a second polycrystalline silicon layer 5 which, in the vicinity of the drain region, covers the first polycrystalline silicon layer 4 and, in the vicinity of the source region, covers the substrate 1. The covering part of the second polycrystalline silicon layer 5 on the first polycrystalline silicon layer 4 is furnished as a control gate, and the part of the substrate 1 nearby the source region is furnished as a select gate. This integral structure of the control gate and select gate have some advantages, in that it improves the efficiency of programming or reading. It is not sensitive to fluctuation of the erase voltage since during reading, it is controlled by the select gate, even if excessive electrons are drawn from the floating gate during erase. With that, problems generated by differences between cells within the same chip are solved.
However, in the structure, since the second polycrystalline silicon layer has coverage according to the first polycrystalline silicon layer, the second polycrystalline silicon layer must have a sufficiently wide width, in consideration of misalignment during the fabrication process. Therefore, it has a disadvantage in that the area of a cell is relatively increased. That disadvantage is a factor against the attainment of large capacity flash EEPROM.
Furthermore, in the drain region of this structure, the second polycrystalline silicon layer is not allowed to cover the outside of the first polycrystalline silicon layer. In consideration of that requirement, self align etching is performed during the fabrication process. But that involves disadvantage in etching the substrate in the source region. If the drain region and the source region are etched separately to avoid the disadvantage, the cell area would be designed to have a larger width.